The present invention relates to a solid state image pickup apparatus whose unit pixel is composed of a photoelectric transducer element, and more particularly, to a solid state image pickup apparatus whose fixed pattern noise (hereafter referred to as FPN) due to the difference in characteristics of amplification elements between each pixel is suppressed, and also to its driving method.
In addition to MOS and CCD type devices, there is known another type solid state image pickup device whose pixel includes an amplification element, such as SIT, AMI, CMD, BASIS, and FGA. This type solid state image pickup device has characteristic features which cannot obtained by solid state image pickup devices, such as MOS and CCD. For example, amplification elements in pixels make it insensitive to noise entering signal lines. Therefore, a high S/N ratio is achievable. Besides, non-destructive read-out is available in this device. While it has the above advantages, it has a drawback that it exhibits large FPN due to the variation in amplification element characteristics between pixels, and this large FPN results in a low S/N ratio.
In view of such high FPN, there are proposed various circuits provided on a chip for suppressing FPN. FIG. 1 shows an example of a configuration of a FPN suppression circuit used in FGA disclosed in Japanese Patent Application Laid-Open No.64-2354 or in "A New Device Architecture Suitable for High-Resolution and High-Performance Image Sensors", IEEE Trans. on ED, Vol. 35, No. 5, May, 1988. In FIG. 1, S is a unit pixel which is one of pixels arranged in 2-dimensional form. There is provided a source line (vertical signal line) to connect amplification elements in common for every column of a pixel array arranged in 2-dimensional form. A FPN suppression circuit is connected for every column. Outputs of the FPN suppression circuits are connected alternately every two column to one of two signal output lines 101 and 102. 103 is a bias transistor, 104 is a capacitor, 105 is a clamping transistor, 106 is a sample-and-hold transistor, 107 is a capacitor, 108 is a switching transistor, and 109 is a horizontal scanning circuit. In this configuration, suppression of FPN is achieved in the following way: That is, during a horizontal blanking interval, the capacitor 107 stores the voltage corresponding to the difference between the signal output obtained after performing of photo integration for a selected row of the pixel array and the output obtained just after the resetting, then, during a horizontal scanning period, the charge stored in the capacitor 107 is read out.
Now, referring to the timing chart in FIG. 2, operation of this suppression circuit will be described. During a period T.sub.1, both of the clamping transistor 105 and sample-and-hold transistor 106 are ON, thus the capacitor 107 is reset and the voltage of node 111 is clamped to a reference voltage Vref. At this time, the signal output including a offset voltage V.sub.0 appears at the other node (node 110) of the capacitor 104. As a result, the capacitor 104 stores the charge described as (V.sub.PS +V.sub.0 -Vref).Co, where V.sub.PS is a voltage increment given by integration. Then, during a period T.sub.2, the clamping transistor 105 is turned off and all pixels of the selected row are reset. At the same time, the sample-and-hold transistor 106 is also turned off. After that, during a period T.sub.3, because each pixel has been just reset, only the off set voltage V.sub.0 including no signal component appears at the node 110. In this state, when the sample-and-hold transistor 106 turns on, the capacitor 107 stores a voltage V' including no offset, given by EQU V'=Co/(C.sub.L +Co).multidot.(Vref-V.sub.PS) (1)
where Co and C.sub.L are capacitances of the capacitors 104 and 107, respectively. This signal is read out during a period T.sub.4. Taking into account a parasitic capacitance C.sub.P of the signal output line 101 (102) , the output voltage V.sub.OUT is given by ##EQU1##
In this way, the signal output with suppressed FPN due to the variation in offset voltage is achieved.
FIG. 3 shows another example of a configuration of a FPN suppression circuit applied for a BASIS, disclosed in Japanese Patent Application Laid-Open No.63-86471. As in the case of FGA, this FPN suppression circuit is also shown just for one pixel S. In FIG. 3, a suppression circuit is provided for every vertical signal line of each column, and the outputs of all suppression circuits are connected in common to a signal output line 201 or 202.
Referring to the timing chart shown in FIG. 4, operation of the above FPN suppression circuit will be described. During a period T.sub.1, resetting of capacitors C.sub.t1 and C.sub.t2 is carried out. During a period T.sub.2, the pixel S is read out and the capacitor C.sub.t1 stores a signal voltage including a offset voltage V.sub.0. Representing a voltage increment in accordance with photo integration by V.sub.PS, the capacitor C.sub.t1 stores a voltage V.sub.t1 given by EQU V.sub.t1 =V.sub.PS +V.sub.0 ( 3)
During a period T.sub.3, resetting of the pixel S is carried out and the photo integration charge stored in the pixel is swept out. During a period T.sub.4, a voltage obtained just after resetting the pixel S is stored in the capacitor C.sub.t2. Here, the voltage V.sub.t2 given to the capacitor C.sub.t2 is described by EQU V.sub.t2 =V.sub.0 ( 4)
During a period T.sub.5, transistors Q.sub.S1 and Q.sub.S2 are turned on so that the charges stored in capacitors C.sub.t1 and C.sub.t2 are connected to the signal output lines 201 and 202, respectively, so as to read out the difference between the voltages of these signal output lines via a differential amplifier 203. Assuming that capacitances of the capacitor C.sub.t1 and C.sub.t2 are C.sub.t1 =C.sub.t2 =C.sub.t, the parasitic capacitance of the signal output lines 201 and 202 is C.sub.P, and the gain of the differential amplifier 203 is 1, the output voltage V.sub.OUT obtained from an output terminal S.sub.OUT is given by ##EQU2##
As described above, the readout signal including a photo charge and the signal obtained just after the photo charge is reset are stored in different capacitors respectively, then by taking the difference between these signals as an output, the suppression of FPN is achieved.
However, the above methods for reducing FPN of solid state image pickup devices have the following problems: First, in both methods, as can be seen from equations (2) and (5) , the parasitic capacitance C.sub.P existing on the signal lines causes the reduction in output voltages. To avoid this reduction, capacitances of the capacitors C.sub.t, C.sub.L, and Co must be sufficiently large compared to the parasitic capacitance C.sub.P. However, the increase in these capacitances requires the increase of the chip area. Secondly, when charges stored in capacitors are read out, the charges are distributed to the parasitic capacitances of the signal lines. As a result, the storage charges are destroyed and it is impossible to perform the non-destructive readout.